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WM8181 12-bit 2MSPS Serial Output CIS/CCD Digitiser
Advanced Information, January 2000, Rev 3.0
DESCRIPTION
The WM8181 is a 12-bit resolution, 2MSPS single channel image digitiser which is designed for easy interface to either CIS or CCD linear image sensors. Data is output in serial mode. The applied clock frequency (MCLK) equals the bit rate of the data output. The sample rate of the WM8181 can be either 1/12th or 1/16th of the applied master clock frequency. The device can be configured for either single-ended or differential input operation. In single ended input mode, a reset clamp voltage can be applied to the analogue signal, under the control of a digital signal at the CLAMP pin. The WM8181 will accept either positive or negative-going video signals at any voltage between AGND and AVDD. The ADC references are internally generated. The range of these references may be derived internally using a bandgap generator or externally using the VREFIN pin. The WM8181 is powered from either 3.3V or 5V single supplies. The device may also be powered from split 5V and 3.3V dual supplies. Typically, the WM8181 consumes 23mA supply current in normal operation. When the device is powered down, the supply current falls to less than 1A. The WM8181 is available in a 16-pin wide-body SOIC package.
FEATURES
* * * * * * * * * * * * 12-bit 2MSPS ADC No missing codes Serial output Simple clocking Internal or external ADC reference range control Accepts positive or negative video Rail to rail input range Reset-level clamp switch 3.3V or 5V single supplies 5V/3.3V dual supplies 23mA supply current 16-pin wide body SOIC package
APPLICATIONS
* * * * * USB bus powered scanners Flatbed scanners Sheetfeed scanners Contact image sensors (CIS) Linear CCDs
BLOCK DIAGRAM
AVDD (16) VSMP (12) MCLK (13)
PD
TIMING AND POWER DOWN CONTROL
WM8181
(15) DVDD VINP (4) SAMPLE/ HOLD VINM (5) (10) DGND CLAMP (11) 0.8*VDD VREFIN (3)
+ x1 VRT/VRB
ADC 12
PARALLEL TO SERIAL
(14) DOUT
1.5V BANDGAP
GENERATOR
(1) (2) AGND1 AGND2
(7) VRT
(6) VRB
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk http://www.wolfson.co.uk
Advanced Information data sheets contain preliminary data on new products in the preproduction phase of development. Supplementary data will be published at a later date.
2000 Wolfson Microelectronics Ltd.
WM8181 PIN CONFIGURATION ORDERING INFORMATION
DEVICE
AGND1 1 16 AVDD
Advanced Information
TEMP. RANGE 0 to 70 C
o
PACKAGE 16-pin SOIC wide body
XWM8181CDW
AGND2 VREFIN
2
15
DVDD DOUT
3
14
VINP
4
13
MCLK
VINM VRB
5 6
12 11
VSMP CLAMP
VRT
7
10
DGND
NC
8
9
NC
PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME AGND1 AGND2 VREFIN VINP VINM VRB VRT NC NC DGND CLAMP VSMP MCLK DOUT DVDD AVDD Ground Digital input Digital input Digital input Digital output Supply Supply TYPE Ground Ground Analogue input Analogue input Analogue input Analogue output Analogue output General analogue ground (0V). Reference analogue ground (0V). Allows external control of the ADC references. Positive video input Negative video input Usually one of VINP or VINM will be an externally applied d.c. bias, the other will be a signal voltage. DESCRIPTION
Lower reference voltage. This pin must be connected to AGND and VRT via decoupling capacitors. See Recommended External Components section for details. Upper reference voltage. This pin must be connected to AGND and VRB via decoupling capacitors. See Recommended External Components section for details. No internal connection No internal connection Digital ground (0V). Connects VINP and VINM together, active high. Video sample synchronisation pulse, at input pixel rate. Sampled on rising edge of MCLK. See Operational Timing Diagrams for details. Master clock. This clock can be applied at either 12 or 16 times the input pixel rate. ADC serial data output, changes on falling edge of MCLK. Digital supply (3.3V, 5V). Analogue supply (3.3V, 5V).
POSSIBLE POWER SUPPLY COMBINATIONS
COMBINATION 1 2 3 AVDD (VOLTS) 5 3.3 5 DVDD (VOLTS) 5 3.3 3.3
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Advanced Information
WM8181
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device.
CONDITION Digital supply voltage: DVDD Analogue supply voltage: AVDD Digital ground: DGND. Analogue ground: AGND1, AGND2 Digital inputs: MCLK, VSMP, CLAMP Digital outputs: DOUT Analogue inputs: VINM, VINP, VREFIN Reference pins: VRT, VRB
MIN GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V
o
MAX GND + 7V GND + 7V GND + 0.3V DVDD + 0.3V DVDD + 0.3V AVDD + 0.3V AVDD + 0.3V
o
Operating temperature range: TA Storage temperature Package body temperature (soldering 10 seconds) Package body temperature (soldering 2 minutes) Notes: 1. GND denotes the voltage of any ground pin.
0C -65 C
o
+70 C +150 C +240 C +183 C
o o o
2. AGND and DGND pins are intended to be operated at the same potential. Differential voltages between these pins will degrade performance.
RECOMMENDED OPERATING CONDITIONS
PARAMETER Operating temperature range Analogue supply voltage (5V) Analogue supply voltage (3.3V) Digital input and output supply voltage SYMBOL TA AVDD AVDD DVDD TEST CONDITIONS MIN 0 4.5 2.97 2.97 5.0 3.3 3.3 TYP MAX 70 5.5 3.63 AVDD UNIT C V V V
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WM8181 ELECTRICAL CHARACTERISTICS
Advanced Information
TEST CHARACTERISTICS AVDD = DVDD = 2.97 to 3.63V and 4.5 to 5.5V, AGND1 = AGND2 = DGND = 0V, TA = 0 to 70C, MCLK = 24MHz unless otherwise stated. PARAMETER ANALOGUE SPECIFICATION 12-bit ADC including Sample and Hold. No Missing Codes Guaranteed. Maximum sample rate Input signal voltage for ADC full-scale (internal reference control) Input signal voltage for ADC full-scale (external reference control) Input signal voltage for ADC zero-scale (internal reference control) Input signal voltage for ADC zero-scale (external reference control) Differential non-linearity Integral non-linearity Analogue Inputs Input voltage limits References: VRT, VRB VRT (internal reference control) VRB (internal reference control) VRT (external reference control) AVDD = 5V AVDD = 3.3V AVDD = 5V AVDD = 3.3V AVDD = 5V AVDD = 3.3V VRB (external reference control) AVDD = 5V AVDD = 3.3V VRT, VRB output leakage Clamp VINM to VINP leakage VINM to VINP resistance VINM to VINP resistance CLAMP low CLAMP high, AVDD = 3.3V VINP = VINM = 2V CLAMP high, AVDD = 5V VINP = VINM = 1.4V <1 50 30 A Power down 2.85 1.70 1.35 0.95 2.10 + VREFIN/2 1.35 + VREFIN/4 2.10 VREFIN/2 1.35 VREFIN/4 <1 A V V V V V V V VINP, VINM 0 AVDD V VINP-VINM MCLK:VSMP ratio = 12:1 2 1.5 MSPS V SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
VINP-VINM
VREFIN
V
VINP-VINM
0
V
VINP-VINM
0
V
DNL INL
0.5 1.5
LSB LSB
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Advanced Information TEST CHARACTERISTICS AVDD = DVDD = 2.97 to 3.63V and 4.5 to 5.5V, AGND1 = AGND2 = DGND = 0V, TA = 0 to 70C, MCLK = 24MHz unless otherwise stated. PARAMETER DIGITAL SPECIFICATION Digital Inputs High level input voltage Low level input voltage High level input current Low level input current Input capacitance Digital Outputs High level output voltage Low level output voltage High impedance output current OVERALL SYSTEM SPECIFICATION Supply Currents Total analogue supply current - active Total digital supply current - active Supply current - disabled AVDD = DVDD = 5V AVDD = DVDD = 3.3V AVDD = DVDD = 5V AVDD = DVDD = 3.3V AVDD = DVDD = 5V AVDD = DVDD = 3.3V t PER MCLK t VSMPSU VSMP t VSMPH SAMPLE n t PD DOUT n-2 D[11] n-2 D[10] tM C L K H tM C L K L 21 19 2 1 <1 <1 IOH = 1mA IOL = -1mA <1 DVDD - 0.5 0.5 VIH VIL <1 <1 5 0.8 DVDD SYMBOL TEST CONDITIONS MIN TYP MAX
WM8181
UNIT
V 0.2 DVDD V A A pF V V A
mA mA mA mA A A
n-2 D[9]
Figure 1 Clock Inputs and Data Output TEST CHARACTERISTICS AVDD = DVDD = 2.97 to 3.63V and 4.5 to 5.5V, AGND1 = AGND2 = DGND = 0V, TA = 0 to 70C, MCLK = 24MHz unless otherwise stated. PARAMETER Maximum MCLK period MCLK high MCLK low VSMP data set-up time VSMP data hold time MCLK to DOUT propagation delay MCLK to DOUT propagation delay SYMBOL tPER tMCLKH tMCLKL tVSMPSU tVSMPH tPD tPD AVDD = DVDD = 5V AVDD = DVDD = 3.3V TEST CONDITIONS MIN 41.7 16 16 10 10 10 15 TYP MAX UNIT ns ns ns ns ns ns ns
Note: Parameters are measured at 50% of the rising/falling edge.
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WM8181
Advanced Information
MCLK
64 MCLK Rising Edges
DON'T CARE
t PZD
VSMP tPZE DOUT t PD
Hi-Z
Hi-Z
Figure 2 Power Down/Power Up TEST CHARACTERISTICS AVDD = DVDD = 2.97 to 3.63V and 4.5 to 5.5V, AGND1 = AGND2 = DGND = 0V, TA = 0 to 70C, MCLK = 24MHz unless otherwise stated. PARAMETER VSMP to DOUT enabled VSMP to DOUT enabled MCLK to DOUT disabled MCLK to DOUT disabled MCLK to DOUT propagation delay MCLK to DOUT propagation delay Note: SYMBOL tPZE tPZE tPZD tPZD tPD tPD AVDD = DVDD = 3.3V AVDD = DVDD = 3.3V AVDD = DVDD = 3.3V TEST CONDITIONS MIN TYP 10 10 10 10 10 15 MAX UNIT ns ns ns ns ns ns
Parameters are measured at 50% of the rising/falling edge.
MCLK
VSMP INPUT t VSU VIDEO (CCD) VIDEO (CIS) t VH
Figure 3 Input Video Timing TEST CHARACTERISTICS AVDD = DVDD = 2.97 to 3.63V and 4.5 to 5.5V, AGND1 = AGND2 = DGND = 0V, TA = 0 to 70C, MCLK = 24MHz unless otherwise stated. PARAMETER Input video set-up time Input video hold time SYMBOL tVSU tVH TEST CONDITIONS MIN TYP 10 20 MAX UNIT ns ns
Notes: 1. tVSU and tRSU denote the set-up time required from when the input video signal has settled. 2. Parameters are measured at 50% of the rising/falling edge. WOLFSON MICROELECTRONICS LTD
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Advanced Information
WM8181
DEVICE DESCRIPTION
INTRODUCTION
The WM8181 is a serial output ADC that is designed to digitise analogue signals directly from CIS and CCD sensors. The reset or reference level and video level from the sensor outputs are sampled using an internal Sample and Hold circuit with an optional black level Clamp. The difference between the sampled levels is passed onto a pipeline ADC with internally generated references where it is converted into a 12-bit digital output. Please refer to the block diagram shown on page 1.
GENERAL OPERATION
SAMPLE AND HOLD
The WM8181 Sample and Hold samples signals from the VINP and VINM inputs. VINM and VINP are connected to the sensor video output and a black level reference. No external buffering is required as long as the input signals have settled before the samples are taken. The black level reference can be provided by either the sensor or a separate circuit. Both inputs are sampled simultaneously and the difference is passed on to the ADC to be converted. For positive-going sensor outputs, VINP is used to input the video signal and VINM is used as the black level reference. For negative-going sensor outputs, VINM is used as the video input and VINP is used as the black level reference.
CLAMP
For a.c. (capacitively) coupled CCD signals, VINP and VINM may be connected together via the optional internal clamp switch, which is controlled by the CLAMP pin. The switch is closed during the reset period of the sensor output and open during the video period, allowing reset level clamping to be performed. This ensures that the input signal is maintained within the input voltage limits of the device, and that the true value of the video signal is processed.
ADC
The ADC converts the differential output from the Sample and Hold into 12-bit digital data ensuring no missing codes in the final digitised output. The 12-bit parallel output from the ADC is transformed into serial format, which is available to the user at the DOUT pin, MSB first.
REFERENCES
The WM8181 has internally generated references, which are controlled via the VREFIN pin. These references are used to set the upper (VRT) and lower limits (VRB) of the ADC range and the fullscale input range (VINP - VINM) of the device. If VREFIN is tied to AVDD, the internal bandgap generator is used to determine the full-scale range. If VREFIN is not tied to AVDD, the full-scale range is determined by the voltage on the VREFIN pin. This is shown in Table 1. The ADC reference voltages, VRT and VRB, are driven onto the VRT and VRB pins by internal amplifiers in the WM8181. Only external decoupling capacitors are required for the VRT and VRB pins. SUPPLY (V) VREFIN (V) REFERENCE CONTROL INPUT VOLTAGE (VINP-VINM) FOR ZERO (0) OUTPUT CODE 0 0 0 0 INPUT VOLTAGE (VINPVINM) FOR FULL-SCALE (+4095) OUTPUT CODE 1.5 VREFIN 1.5 VREFIN
5 5 3.3 3.3 Table 1
AVDD 0.5 - 2 AVDD 0.75 - 1.5
Internal External Internal External
VREFIN and ADC Input Voltage Requirements for Internal and External Reference Control
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WM8181
OVERALL TIMING
Advanced Information
The WM8181 input sampling, conversion and data output is controlled by externally applied MCLK and VSMP clocks. Please refer to the Operational Timing Diagrams (Figures 4 and 5) shown at the end of this section.
12:1 MCLK: VSMP RATIO OPERATION
MCLK can run at speeds of up to 24MHz. VSMP is a pulse one MCLK period long, with 12 times the period of MCLK. VSMP must cover one rising edge of MCLK. If VSMP is high for more than one MCLK rising edge, the last MCLK rising edge that is covered is defined as the starting point and the video signal will be sampled on the next rising edge of MCLK. Output data being processed at this time may be corrupted. VSMP should be held low for 11 MCLK rising edges, then pulsed high for the 12th MCLK rising edge to produce an MCLK:VSMP ratio of 12:1. If VSMP is held low for less than 11 MCLK rising edges, the device will reset to the starting point and the video signal will be sampled on the next rising edge of MCLK. Output data being processed during this time may be corrupted.
16:1 MCLK: VSMP RATIO OPERATION
The WM8181 can also operate with an MCLK:VSMP ratio of 16:1. Video signal sampling is performed in the same manner as in 12:1 operation except that the device will wait an extra four MCLK periods for the next VSMP pulse to go low before sampling the video signal.
DEVICE LATENCY
For 12:1 operation, the WM8181 will start to output valid data MSB first on the falling edge of MCLK 24.5 MCLK periods after the sampling instant (first rising edge of MCLK after VSMP goes low) for that pixel. The device continues to output the data on the next 11 falling edges of MCLK For 16:1 operation, the output latency increases to 32.5 MCLK periods after the sampling instant. Data is output MSB first on this falling edge of MCLK, and continues over the next 11 falling edges of MCLK. The four bits between the end of one output and the start of the next will be 0.
POWER DOWN
If VSMP is held high for 64 MCLK rising edges, the device will power down, causing DOUT, VRT, and VRB to change into a high impedance state. The device will start powering up immediately on VSMP going low, however VRT and VRB will take some time to recover and settle, depending on how their voltages have decayed during power down and the decoupling capacitors used. Typically for 1F decoupling capacitors the amount of time taken for VRT and VRB to recover may be up to 10ms. If 0.1F capacitors are used, this time will decrease to typically 1ms.
OPERATIONAL TIMING DIAGRAMS
CCD Outputs Video Pixel 0 Reset Video Pixel 1 Reset Video Pixel 2 Reset Video Pixel 3
MCLK
VSMP
S/H LATENCY = 24.5 MCLK PERIODS DOUT D11 D0 PIXEL - 2 D11 D0 PIXEL - 1 D11 D0 PIXEL 0
Figure 4 12:1 Operation
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Advanced Information
WM8181
Reset Video Pixel 1 Reset Video Pixel 2 Reset Video Pixel 3
CCD Outputs
Video Pixel 0
MCLK
VSMP
S/H LATENCY = 32.5 MCLK PERIODS D11 D0 PIXEL - 2 0000 D11 D0 PIXEL - 1 0000 D11 D0 PIXEL 0 0000
DOUT
Figure 5 16:1 Operation
APPLICATIONS RECOMMENDATIONS
INTRODUCTION
The WM8181 is a mixed signal device, therefore careful PCB layout is required. The following section contains PCB layout guidelines, which are recommended for optimal performance from the WM8181, and some typical application circuits.
PCB LAYOUT
1) 2) 3) 4) Use separate analogue and digital power and ground planes. The analogue and digital ground planes should be connected as close as possible to, or underneath, the WM8181. Place all supply decoupling capacitors as close as possible to their respective supply pins and provide a low impedance path from the capacitors to the appropriate ground. Avoid noise on AGND pins 1 and 2. Avoid noise on reference pins VRT and VRB. Place the decoupling capacitors as close as possible to these pins and provide a low impedance path from the capacitors to analogue ground. When VREFIN is used as an external reference control, any noise on VREFIN will degrade the performance of the ADC. In this case, VREFIN must be carefully de-coupled to AGND. Minimise load capacitance on digital output DOUT. Capacitive loads of greater than 20pF will degrade performance. Use buffers if necessary and keep tracks short.
5) 6)
TYPICAL APPLICATIONS
The WM8181 is intended for colour scanner applications using a line-by-line architecture and monochrome scanners, as used in fax machines. The low pincount and simple digital interface gives the scanner designer the opportunity to place the ADC near to the sensor. This allows the video information to be converted into the digital domain as early as possible in the signal chain and minimises analogue noise problems. In the typical architecture of a flatbed scanner, this means that only power and digital signals appear on the ribbon minimising crosstalk between the digital clocks and analogue video signals. Care must be taken to avoid any increase in EMI generated by the higher clock rates on the ribbon cable.
CIS SCANNER
The WM8181 is ideal for use in CIS based scanners where the video output is supplied on a single output pin. This is true of the majority of colour CIS and all monochrome CIS. In general, CIS devices provide a video output that becomes more positive for more illumination. This situation corresponds to the d.c. Coupled Positive Video diagram, Figure 6. The value of the black reference voltage should be set to be slightly less than the black level output from the CIS to ensure that the black never saturates. WOLFSON MICROELECTRONICS LTD
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WM8181
VOUT
Advanced Information
VINP MCLK
CIS SENSOR
VSMP
WM8181
DOUT BLACK REFERENCE LEVEL
SYSTEM ASIC
VINM VREFIN VRT
CLAMP VRB
EXACT CIRCUITRY MAY VARY DEPENDING ON SENSOR USED SET VOLTAGE TO MATCH V PP F R O M SENSOR OR TIE TO AVDD TO SET FULL-SCALE INPUT TO 1.5V
Figure 6 d.c. Coupled Positive Video Some of the newer CIS devices have a reference voltage that corresponds closely to the black level. In most cases this reference voltage cannot be applied directly to the VINM pin because the black video output can go below this value and will be outside the range of the ADC. To overcome this, VINM should be driven from a voltage that is slightly more negative than the CIS reference voltage. This is shown in Figure 7. The input current to VINM is small but care should be taken to ensure that R2 and R3 do not load the CIS reference circuit.
VOUT
VINP MCLK
CIS SENSOR
V REF
VSMP
WM8181
DOUT
SYSTEM ASIC
VINM VREFIN VRT
CLAMP VRB
EXACT CIRCUITRY MAY VARY DEPENDING ON SENSOR USED S E T V O L T A G E T O M A T C H VPP F R O M SENSOR OR TIE TO AVDD TO SET FULL-SCALE INPUT TO 1.5V
Figure 7 CIS with Reference Voltage WOLFSON MICROELECTRONICS LTD
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Advanced Information
WM8181
The differential nature of the WM8181 allows it to interface as easily to CCD sensors as to CIS. The negative going video simply requires that the VINP and VINM pins are swapped over so that the video signal is applied to VINM and the reference voltage is applied to VINP. The d.c. level of the CCD output must lie within the input limits of the WM8181. A level shifter may be required to ensure this. See Figure 8.
CCD SCANNER
LEVEL SHIFT DEPENDENT ON V OUT DC LEVEL
BLACK REFERENCE LEVEL
WM8181
VINP
MCLK
VSMP V OUT
LEVEL SHIFT
DOUT
SYSTEM ASIC
CCD SENSOR
VINM VREFIN VRT
CLAMP VRB
SET VOLTAGE TO MATCH V PP F R O M S E N S O R .
Figure 8 d.c. Coupled Negative Video
USING THE INTERNAL CLAMP
When using a CCD it is recommended that the designer use a.c. (capacitive) coupling between the CCD output buffer and the input to the WM8181, shown in Figure 9. A CCD sensor has a negative going video signal superimposed on a d.c. voltage of around 6V. The series capacitor between the CCD buffer and the input to the WM8181 removes this large d.c. voltage while still allowing the video signal through.
4.7k
WM8181
VINP
220n
MCLK
4.7k
VSMP
DOUT V OUT
200p
SYSTEM ASIC
VINM VREFIN VRT
CLAMP VRB
CCD SENSOR
SET VOLTAGE TO MATCH VPP F R O M S E N S O R .
Figure 9 a.c. Coupled Negative Video WOLFSON MICROELECTRONICS LTD
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WM8181
Advanced Information During the reset period of the video waveform the user applies a logic high signal to the CLAMP pin, connecting the VINP pin to the VINM pin. This is illustrated in Figure 10. This has the effect of charging, or discharging, the VINM side of the coupling capacitor to the black reference voltage applied to VINP. When the CLAMP pin is taken low again the voltage across the capacitor will stay at a fixed value and the input to the WM8181 will follow the output from the CCD. The WM8181 therefore converts the true value of the video signal, VRS - VVS.
VRS
V ID E O S IG N A L
V VS
CLAM P S W IT C H
O PEN
C LO S E D
O PEN
C LO S E D
O PEN
C LO S E D
CLAM P
Figure 10 Clamp Switch Operation.
ADJUSTING THE ADC INPUT RANGE
The WM8181 normally uses an internal bandgap reference to generate the ADC reference voltages. With the recommended decoupling on the VRT and VRB pins, this ensures that the ADC receives the cleanest reference voltages and thus achieves the optimum performance. The full scale input range of the ADC is fixed in this mode to be 1.5V and is largely independent of supply voltage variations. VREFIN should be connected to AVDD in this case. It is possible to adjust the input range of the ADC by applying an externally generated voltage to the VREFIN pin. The value of the ADC references and the corresponding input range of the ADC can be determined from Table 1 in the Device Description section of this datasheet. Care must be taken to avoid any noise on the VREFIN pin, as any noise on this pin with respect to AGND will degrade the performance of the WM8181.
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Advanced Information
WM8181
RECOMMENDED EXTERNAL COMPONENTS
DVDD 15 C1 10 DGND AGND1 AGND2 4 5 1 2 DVDD AVDD 16
AVDD
C2
Video Inputs Clamp Control Timing Signals Reference Control
N O T E S : 1. C 1 to C 6 should be fitted as close to WM8181 as possible. 2. A G N D a n d D G N D s h o u l d b e c o n n e c t e d as close to WM8181 as possible.
VINP VINM
DVDD + C7 DGND 14
AVDD + C8 AGND
WM8181
11
CLAMP
13 12
MCLK VSMP
DOUT
Output Data
3
VRT VREFIN
7 C3 C4
References
VRB
6 C5 C6
AGND
Figure 6 Recommended External Components Diagram COMPONENT REFERENCE C1 C2 C3 C4 C5 C6 C7 C8 SUGGESTED VALUE 0.1F 0.1F 0.1F 1F 0.1F 0.1F 10F 10F Decoupling for DVDD. Decoupling for AVDD. High frequency decoupling between VRT and VRB. Low frequency decoupling between VRT and VRB (non-polarised, optional). Decoupling for VRB. Decoupling for VRT. Reservoir capacitor for DVDD. Reservoir capacitor for AVDD. DESCRIPTION
Table 2 External Components Description
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WM8181 PACKAGE DIMENSIONS
DW: 16 PIN SOICW 7.5mm (0.3") Wide Body, 1.27mm Lead Pitch
Advanced Information
DM019.A
e
B
16
9
E
H
L
1 8
D
h x 45 o
A1 -CA
SEATING PLANE
C
0.10 (0.004)
Symbols A A1 B C D e E h H L REF:
Dimensions (mm) MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 10.10 10.50 1.27 BSC 7.40 7.60 0.25 0.75 10.00 10.65 0.40 1.27 o o 0 8
Dimensions (Inches) MIN MAX 0.0926 0.1043 0.0040 0.0118 0.0130 0.0200 0.0091 0.0125 0.3465 0.3622 0.0500 BSC 0.2914 0.2992 0.0100 0.0290 0.3940 0.4190 0.0160 0.0500 o o 0 8
JEDEC.95, MS-013
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES). B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN). D. MEETS JEDEC.95 MS-013, VARIATION = AA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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